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Dr. Zijiang (James) Yang
Assistant Professor
Department of Computer Science
College of Engineering and Applied Science
Western Michigan University

Research

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My primary research interest is computer system reliability, which spans the spectrum from hardware design automation to software engineering. I am interested in all approaches leading to reliable hardware and software systems. I am particularly interested in model checking techniques to improve software reliability. You can find my publication here.
 
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Verification of Multi-Threaded Programs

The ever increasing use of hyperthreading as well as the availability of inexpensive multiprocessor hardware present tremendous opportunities as well as serious challenges for software developers. Today, hyperthreading and multicore hardware have become ubiquitous, which puts us at a fundamentalturning point in software development. In order for software applications to benefit from the continued exponential throughput advances in new processors, the applications must be well-written multi-threaded software programs. Unfortunately, writing multi-threaded software programs that can unleash the full potential of present and future hardware systems remains as challenging today as it was thirty years ago. In this project we aim to develop practical tools and methodologies that can bring down the complexity of testing/debugging multi-threaded programs to a level comparable to that of testing/debugging sequential programs

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Automatic Bug Fixing for Concurrent Programs

It is a challenge task to debug single-processor-based multi-threaded programs. The problem is exacerbated on multi-processor systems where the instructions in an thread may be reordered. Because the resulting executions are counterintuitive and nondeterministic, even highly skilled programmers are likely to create programming bugs
and feel challenged to fix them. Over the course of the project, we will design and implement novel algorithms
to automatically fix bugs caused by the reordering in the execution of program statements by automatically inserting memory fence instructions.