____________________________________________________________________________
|           +-----+ R                                                      |
|     ||<-->| PC  | e                                                      |
|     ||<-->| SP  | g       CCCC  PPPP  U  U                               |
|     ||<-->| PSW | i      C     P  P  U  U                                |
|   R ||<-->| Tick| s     C     PPPP  U  U                                 |
|   e ||<-->| R0  | t    C     P     U  U                                  |
|   g ||<-->| R1  | e   CCCC  P     UUUU                                   |
|   i || ...| ... | r                                                      |
|   s ||<-->| Rn  | s                                                      |
|   t ||    +-----+                                                        |
|   e ||                                                 Memory Registers  |
|   r ||  Bus      ________________  interupt            +-------------+   |
|     ||<*********>| CU           |<---------------||<-> | Control     |   |
|   B ||  Control  | Control UNit |  ill memory op ||--> | Address     |   |
|   u ||           |           *  |  or page fault ||<-> | Data        |   |
|   s ||           |___________*__|                ||    +-------------+   |
|     ||  (PC)                 *     address and   ||          /\          |
|     ||---------->____________V___--control (rt)->||          ||          |
|     ||           | fetch     *  |                ||          ||          |
|     ||  (PC++)   | instruction  |  data          ||          \/          |
|     ||<----------|___________*__|<---------------||  __________________  |
|     ||               |       *                   ||  |                |  |
|     ||               V       *                 M ||  |                |  |
|     ||           +--------+  *               I e ||  |    L1 Cache    |  |
|     ||           | IR     |  *               n m ||  |                |  |
|     ||           +--------+  * CU control    t o ||  |                |  |
|     ||               |       *               e r ||  |                |  |
|     ||               V       *               r y ||  |                |  |
|     ||           ____________V___  interupt  n   ||  |                |  |
|     ||           | decode       |--> to CU   a B ||  |                |  |
|     ||           | instruction  |  ill inst  l u ||  |                |  |
|     ||           |___________*__|              s ||  |                |  |
|     ||                  ||   *                   ||  |                |  |
|     ||                  \/   *     address and   ||  |________________|  |
|     ||---------->____________V___--control (rd)->||          /\          |
|     ||           | load from Mem|                ||          ||          |
|     ||           | source       |  data          ||          ||          |
|     ||<----------|___________*__|<---------------||          \/          |
|     ||                  ||   *                   ||  __________________  |
|     || operand1         \/   *                   ||  |                |  |
|     ||---------->____________V___                ||  |                |  |
|     || operand2  |              |  interupt      ||  |      MMU       |  |
|     ||---------->|     ALU      |--> to CU       ||  |                |  |
|     ||           |              |  on Errors     ||  |   Memory       |  |
|     ||  result1  | Arithmetic   |                ||  |   Management   |  |
|     ||<----------| Logic        |                ||  |   Unit         |  |
|     ||  result2  | UNit         |                ||  |                |  |
|     ||<----------|___________*__|                ||  |                |  |
|     ||                  ||   *                   ||  |                |  |
|     ||                  \/   *     address and   ||  |                |  |
|     ||---------->____________V___--control (wd)->||  |________________|  |
|     ||           | store to mem |                ||      ||||            |
|     ||           | destination  |  data          ||      ||||            |
|                  |______________|--------------->||      ||||            |
|   Internal Clock                                         ||||            |
|________||______________|_________________________________||||_____|______|
         ||              |                                 ||||     |
    External Clock     Reset  ...          External Memory ||||   Power
                                                 Bus